<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\IP\gowin_sp\RAM.v<br>
D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\riscv32.v<br>
D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\riscv32_alu.v<br>
D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\top.v<br>
D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\uart_debug.v<br>
D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\uart_memory.v<br>
D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\uart_recv.v<br>
D:\GaoYun_pro\gaoyun_cpu\GY_riscv\src\uart_txd.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.06-1</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Nov 26 14:56:00 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.326s, Peak memory usage = 214.605MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.557s, Peak memory usage = 214.605MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 214.605MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.246s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 22s, Elapsed time = 0h 0m 22s, Peak memory usage = 214.605MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.415s, Peak memory usage = 214.605MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.19s, Peak memory usage = 214.605MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 25s, Elapsed time = 0h 0m 24s, Peak memory usage = 214.605MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>24</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>22</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>12</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>855</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>50</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>405</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>168</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>34</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>67</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>122</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>2902</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>233</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>765</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>1904</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>272</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>272</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>9</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>9</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>9</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSP</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>3183(2911 LUTs, 272 ALUs) / 8640</td>
<td>37%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>855 / 6693</td>
<td>13%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 6693</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>855 / 6693</td>
<td>13%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>9 / 26</td>
<td>35%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>50.0(MHz)</td>
<td>61.3(MHz)</td>
<td>14</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.674</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>17.271</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.945</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>75</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/I1</td>
</tr>
<tr>
<td>3.328</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/COUT</td>
</tr>
<tr>
<td>3.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/CIN</td>
</tr>
<tr>
<td>3.385</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>3.385</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>3.442</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>3.442</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>3.499</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>3.499</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>3.556</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>3.556</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>3.613</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>3.613</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>3.670</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>3.670</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>3.727</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>3.727</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>3.784</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>3.784</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>3.841</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>3.841</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>3.898</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>3.898</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>3.955</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>3.955</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>4.012</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>4.012</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>4.069</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>4.069</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>4.126</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>4.126</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>4.183</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>4.183</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>4.240</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>4.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>4.297</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>4.297</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>4.354</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>4.354</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>4.411</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>4.411</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>4.468</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>4.468</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>4.525</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>4.525</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>4.582</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>4.582</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>4.639</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>4.639</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>4.753</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>4.753</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>4.810</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>4.810</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>4.867</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>4.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>4.924</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>4.924</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>4.981</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>5.461</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>6.283</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>6.763</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/I2</td>
</tr>
<tr>
<td>7.585</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/F</td>
</tr>
<tr>
<td>8.065</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I1</td>
</tr>
<tr>
<td>9.164</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>9.644</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>10.676</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>11.156</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/I0</td>
</tr>
<tr>
<td>12.188</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/F</td>
</tr>
<tr>
<td>12.668</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/I0</td>
</tr>
<tr>
<td>13.700</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/F</td>
</tr>
<tr>
<td>14.180</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6878_s9/I0</td>
</tr>
<tr>
<td>15.212</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6878_s9/F</td>
</tr>
<tr>
<td>15.692</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6878_s7/I1</td>
</tr>
<tr>
<td>16.791</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6878_s7/F</td>
</tr>
<tr>
<td>17.271</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_5_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_5_s1/CLK</td>
</tr>
<tr>
<td>20.945</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_5_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 10.668, 66.983%; route: 4.800, 30.139%; tC2Q: 0.458, 2.878%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.674</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>17.271</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.945</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>75</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/I1</td>
</tr>
<tr>
<td>3.328</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/COUT</td>
</tr>
<tr>
<td>3.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/CIN</td>
</tr>
<tr>
<td>3.385</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>3.385</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>3.442</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>3.442</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>3.499</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>3.499</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>3.556</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>3.556</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>3.613</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>3.613</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>3.670</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>3.670</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>3.727</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>3.727</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>3.784</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>3.784</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>3.841</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>3.841</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>3.898</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>3.898</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>3.955</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>3.955</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>4.012</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>4.012</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>4.069</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>4.069</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>4.126</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>4.126</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>4.183</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>4.183</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>4.240</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>4.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>4.297</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>4.297</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>4.354</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>4.354</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>4.411</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>4.411</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>4.468</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>4.468</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>4.525</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>4.525</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>4.582</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>4.582</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>4.639</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>4.639</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>4.753</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>4.753</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>4.810</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>4.810</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>4.867</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>4.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>4.924</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>4.924</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>4.981</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>5.461</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>6.283</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>6.763</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/I2</td>
</tr>
<tr>
<td>7.585</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/F</td>
</tr>
<tr>
<td>8.065</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I1</td>
</tr>
<tr>
<td>9.164</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>9.644</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>10.676</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>11.156</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/I0</td>
</tr>
<tr>
<td>12.188</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/F</td>
</tr>
<tr>
<td>12.668</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/I0</td>
</tr>
<tr>
<td>13.700</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/F</td>
</tr>
<tr>
<td>14.180</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6860_s9/I0</td>
</tr>
<tr>
<td>15.212</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6860_s9/F</td>
</tr>
<tr>
<td>15.692</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6860_s7/I1</td>
</tr>
<tr>
<td>16.791</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6860_s7/F</td>
</tr>
<tr>
<td>17.271</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1/CLK</td>
</tr>
<tr>
<td>20.945</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 10.668, 66.983%; route: 4.800, 30.139%; tC2Q: 0.458, 2.878%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.674</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>17.271</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.945</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_17_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>75</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/I1</td>
</tr>
<tr>
<td>3.328</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/COUT</td>
</tr>
<tr>
<td>3.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/CIN</td>
</tr>
<tr>
<td>3.385</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>3.385</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>3.442</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>3.442</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>3.499</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>3.499</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>3.556</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>3.556</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>3.613</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>3.613</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>3.670</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>3.670</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>3.727</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>3.727</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>3.784</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>3.784</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>3.841</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>3.841</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>3.898</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>3.898</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>3.955</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>3.955</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>4.012</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>4.012</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>4.069</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>4.069</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>4.126</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>4.126</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>4.183</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>4.183</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>4.240</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>4.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>4.297</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>4.297</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>4.354</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>4.354</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>4.411</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>4.411</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>4.468</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>4.468</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>4.525</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>4.525</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>4.582</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>4.582</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>4.639</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>4.639</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>4.753</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>4.753</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>4.810</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>4.810</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>4.867</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>4.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>4.924</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>4.924</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>4.981</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>5.461</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>6.283</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>6.763</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/I2</td>
</tr>
<tr>
<td>7.585</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/F</td>
</tr>
<tr>
<td>8.065</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I1</td>
</tr>
<tr>
<td>9.164</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>9.644</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>10.676</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>11.156</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/I0</td>
</tr>
<tr>
<td>12.188</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/F</td>
</tr>
<tr>
<td>12.668</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/I0</td>
</tr>
<tr>
<td>13.700</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/F</td>
</tr>
<tr>
<td>14.180</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6854_s9/I0</td>
</tr>
<tr>
<td>15.212</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6854_s9/F</td>
</tr>
<tr>
<td>15.692</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6854_s7/I1</td>
</tr>
<tr>
<td>16.791</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6854_s7/F</td>
</tr>
<tr>
<td>17.271</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_17_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_17_s1/CLK</td>
</tr>
<tr>
<td>20.945</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_17_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 10.668, 66.983%; route: 4.800, 30.139%; tC2Q: 0.458, 2.878%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.674</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>17.271</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.945</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>75</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/I1</td>
</tr>
<tr>
<td>3.328</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/COUT</td>
</tr>
<tr>
<td>3.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/CIN</td>
</tr>
<tr>
<td>3.385</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>3.385</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>3.442</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>3.442</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>3.499</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>3.499</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>3.556</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>3.556</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>3.613</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>3.613</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>3.670</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>3.670</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>3.727</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>3.727</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>3.784</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>3.784</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>3.841</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>3.841</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>3.898</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>3.898</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>3.955</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>3.955</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>4.012</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>4.012</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>4.069</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>4.069</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>4.126</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>4.126</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>4.183</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>4.183</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>4.240</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>4.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>4.297</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>4.297</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>4.354</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>4.354</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>4.411</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>4.411</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>4.468</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>4.468</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>4.525</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>4.525</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>4.582</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>4.582</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>4.639</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>4.639</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>4.753</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>4.753</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>4.810</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>4.810</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>4.867</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>4.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>4.924</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>4.924</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>4.981</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>5.461</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>6.283</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>6.763</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/I2</td>
</tr>
<tr>
<td>7.585</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/F</td>
</tr>
<tr>
<td>8.065</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I1</td>
</tr>
<tr>
<td>9.164</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>9.644</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>10.676</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>11.156</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/I0</td>
</tr>
<tr>
<td>12.188</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/F</td>
</tr>
<tr>
<td>12.668</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/I0</td>
</tr>
<tr>
<td>13.700</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/F</td>
</tr>
<tr>
<td>14.180</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6834_s8/I0</td>
</tr>
<tr>
<td>15.212</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6834_s8/F</td>
</tr>
<tr>
<td>15.692</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6834_s7/I1</td>
</tr>
<tr>
<td>16.791</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6834_s7/F</td>
</tr>
<tr>
<td>17.271</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1/CLK</td>
</tr>
<tr>
<td>20.945</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 10.668, 66.983%; route: 4.800, 30.139%; tC2Q: 0.458, 2.878%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.741</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>17.204</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.945</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_23_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>75</td>
<td>picorv32_core/riscv32_alu_u1/op2num_0_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/I1</td>
</tr>
<tr>
<td>3.328</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s64/COUT</td>
</tr>
<tr>
<td>3.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/CIN</td>
</tr>
<tr>
<td>3.385</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>3.385</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>3.442</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>3.442</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>3.499</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>3.499</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>3.556</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>3.556</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>3.613</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>3.613</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>3.670</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>3.670</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>3.727</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>3.727</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>3.784</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>3.784</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>3.841</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>3.841</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>3.898</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>3.898</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>3.955</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>3.955</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>4.012</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>4.012</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>4.069</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>4.069</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>4.126</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>4.126</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>4.183</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>4.183</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>4.240</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>4.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>4.297</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>4.297</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>4.354</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>4.354</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>4.411</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>4.411</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>4.468</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>4.468</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>4.525</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>4.525</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>4.582</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>4.582</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>4.639</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>4.639</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>4.753</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>4.753</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>4.810</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>4.810</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>4.867</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>4.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>4.924</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>4.924</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>4.981</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>5.461</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>6.283</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>6.763</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/I2</td>
</tr>
<tr>
<td>7.585</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s79/F</td>
</tr>
<tr>
<td>8.065</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I1</td>
</tr>
<tr>
<td>9.164</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>9.644</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>10.676</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>11.156</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/I0</td>
</tr>
<tr>
<td>12.188</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/F</td>
</tr>
<tr>
<td>12.668</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/I0</td>
</tr>
<tr>
<td>13.700</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>picorv32_core/riscv32_alu_u1/n6828_s15/F</td>
</tr>
<tr>
<td>14.180</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6842_s8/I0</td>
</tr>
<tr>
<td>15.212</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6842_s8/F</td>
</tr>
<tr>
<td>15.692</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6842_s7/I0</td>
</tr>
<tr>
<td>16.724</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n6842_s7/F</td>
</tr>
<tr>
<td>17.204</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_23_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_23_s1/CLK</td>
</tr>
<tr>
<td>20.945</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_23_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 10.601, 66.844%; route: 4.800, 30.266%; tC2Q: 0.458, 2.890%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>
